这是几种接口的标准电平

这是⼏种接⼝的标准电平。LVTTL

The LVTTL standard is a single-ended, general-purpose standard for 3.3-V applications. The maximumrecommended input voltage for Mercury devices is 4.1 V, which exceeds the 3.9-V requirement of thisspecification. This standard requires the output buffer to drive to 2.4 V (minimum V OH = 2.4 V) but doesnot require the use of input reference voltages or termination. The LVTTL interface is defined by JEDECStandard JESD 8-A, Interface Standard for Nominal 3.0 V/3.3 V Supply Digital Integrated Circuits.LVCMOS

LVCMOS is a single-ended general-purpose standard used for 3.3-V applications. The input bufferrequirements are the same as the LVTTL requirements, and the output buffer is required to drive to therail (minimum V OH = V CCIO – 0.2 V). This standard requires a 3.3-V I/O supply voltage (V CCIO ), butnot the use of input reference voltages or termination. The LVCMOS standard is defined in JEDECStandard JESD 8-A, Interface Standard for Nominal 3.0 V/3.3 V Supply Digital Integrated Circuits.2.5 V

The 2.5-V standard is similar to LVCMOS but is used for 2.5-V power supply levels. Mercury devicesmeet the normal range of this specification. This standard requires a 2.5-V V CCIO , but not the use ofinput reference voltages or termination. The 2.5-V I/O standard is documented by JEDEC StandardJESD 8-5, 2.5 V ±0.2 V (Normal Range) and 1.7 V to 2.7 V (Wide Range) Power Supply Voltage andInterface Standard for Nonterminated Digital Integrated Circuit.

1.8 V

The 1.8-V I/O standard is similar to LVCMOS but is used for 1.8-V power supply levels and reduced inputand output thresholds. Mercury devices meet the normal range of this specification. This standardrequires a 1.8-V V CCIO , but not the use of input reference voltages or termination. The 1.8-V I/O

standard is documented by JEDEC Standard JESD 8-7, 1.8 V ±0.15 V (Normal Range) and 1.2 V to 1.95V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital IntegratedCircuit.

3.3-V PCI

Mercury devices are compliant with PCI Local Bus Specification, Revision 2.2 for 3.3-V operation. At 3.3V, the PCI standard supports up to 64-bit bus width operation at 33 or 66 MHz. This standard usesLVTTL-type input and output buffers and requires a 3.3-V V CCIO , but not the use of input referencevoltages or termination.

PCI-X

An enhanced version of the PCI specification that can support higher average bandwidth, PCI-X hasmore stringent requirements than PCI. PCI-X provides backward compatibility by allowing devices tooperate at conventional PCI frequencies (33 MHz and 66 MHz).

LVDS

The LVDS I/O standard is used for very high-performance, low-power- consumption data transfer. Twokey industry standards define LVDS: IEEE 1596.3 SCI-LVDS and ANSI/TIA/EIA-644. Both standardshave similar key features, but the IEEE standard supports a maximum data transfer of 250 megabits persecond (Mbps). Mercury devices are designed to meet the ANSI/TIA/EIA-644 requirements at up to 840Mbps using source syncronous mode, and up to 1.25 Gbps in CDR mode. The LVDS standard requires a3.3-V V CCIO and a 100-??termination resistor between the two traces at the input buffer. No inputreference voltage is required.

LVPECL

The LVPECL standard is used in video graphic, telecommunications, and data communication designs.It is also used for clock distribution.LVPECL is a differential I/O standard that is similar to LVDS, but witha different common mode and differential voltage. The LVPECL standard requires a 3.3-V V CCIO and a100-??termination resistor between the two traces at the input buffer. No input reference voltage isrequired.

PCML

PCML is a differential standard used for high-speed interfacing. PCML requires a 3.3-V V CCIO and a

100-??termination resistor between the two traces at the input buffer. In addition, each input tracerequires a 50-??resistor to V TT , and each output trace requires a 100-??resistor to V TT . No inputreference voltage is required.GTL+The GTL+ standard is a high-speed bus standard first used by Intel Corporation for interfacing with thePentium Pro processor. GTL+ is a voltage-referenced standard requiring a 1.0-V input V REF and a 1.5-V V TT . Because GTL+ is an open-drain standard, it does not require a particular V CCIO supplyvoltage. GTL+ is often used for processor interfacing or communication across a backplane.HSTL Class I, II, III & IVThe HSTL standard is a 1.5-V output buffer supply voltage-based interface standard for digital integratedcircuits. HSTL is a voltage-referenced standard requiring a 0.75-V V REF , a 1.5-V V CCIO , and a 0.75-VV TT . HSTL class III and IV require a 0.9-V V REF , a 1.5-V V CCIO , and a 1.5-V V TT .The HSTLstandard is specified by JEDEC Standard JESD 8-6, High-Speed Transceiver Logic (HSTL).SSTL-2 Class I & IIThe SSTL-2 standard is a voltage-referenced standard requiring a 1.125-V V REF , a 2.5-V V CCIO , anda 1.125-V V TT . SSTL-2 is used for high-speed SDRAM interfaces. The SSTL-2 I/O standard isspecified by JEDEC Standard JESD 8-9, Stub-Series Terminated Logic for 2.5 Volts (SSTL-2).SSTL-3 Class I & IIThe SSTL-3 standard is a voltage-referenced standard requiring a 1.5-V V REF , a 3.3-V V CCIO , and a1.5-V V TT . SSTL-3 is used for high-speed SDRAM interfaces. The SSTL-3 I/O standard is specified byJEDEC Standard JESD 8-8, Stub-Series Terminated Logic for 3.3 Volts (SSTL-3).AGPMercury devices support the AGP interface in both ??and ??modes. AGP ??is a voltage-referencedstandard requiring a 1.32-V V REF , and a 3.3-V V CCIO . This I/O standard does not require termination.The AGP standard is specified by the Advanced Graphics Port Interface Specification Revision 2.0introduced by Intel Corporation for graphics applications.CTTCTT is a voltage-referenced standard requiring a 1.5-V V REF , a 3.3-V V CCIO , and a 1.5-V V TT . CTTdrivers, when not terminated, are compatible with the AC and DC specifications for LVCMOS andLVTTL. The CTT standard is specified by JEDEC Standard JESD 8-4, Center-Tap-Terminated (CTT)Low-Level, High-Speed Interface Standard for DigitalIntegrated Circuits.++++++I/O电平标准：1 单端标准 LVTTL LVCMOS 静态功耗低，不适⽤于⾼速（>150MHz）电路中，以地作为参考。2 差分标准 LVDS LVPECL CML LVDS满常⽤的。3 伪差分标准 SSTL HSTL主要⽤在⾼速的存储器接⼝上，如 DDR SDRAM,速率可到600Mbit/s。 LVDS与PECL、LVPECL、CML、RS-422及单端器件之间的接⼝设计上⽹时间 : 2005年06⽉20⽇ 收藏 打印版 推荐给同仁 发送查询图1：PECL/LVPECL到LVDS的接⼝电路。低电压差分信号(LVDS)在对信号完整性、低抖动及共模特性要求较⾼的系统中得到了⼴泛的应⽤。本⽂针对LVDS与其他⼏种接⼝标准之间的连接，对⼏种典型的LVDS接⼝电路进⾏了讨论。如今对⾼速数据传输的需求正推动着接⼝技术向⾼速、串⾏、差分、低功耗以及点对点接⼝的⽅向发展，⽽低电压差分信号(LVDS)具备所有这些特性。Pericom半导体公司可提供多种LVDS驱动器、接收器以及时钟分配缓冲器芯⽚。本⽂将讨论LVDS与正射极耦合逻辑(PECL)、低电压正射极耦合逻辑(LVPECL)、电路模式逻辑(CML)、RS-422以及单端器件之间采⽤电阻⽹络的接⼝电路设计。图2：调整电路，R1＝(VR1＋R1a)，R2＝(VR2＋R2a)，R3＝(VR3＋R3a)。因为各⼚商所提供的驱动器与接收器的结构不⼀样，所以本⽂提供的电路仅供设计时参考。设计者需要对电路进⾏验证，并调节电路中的电阻和电容值以获得最佳性能。电阻分压器的计算表1列出了本⽂所采⽤的不同接⼝标准的⼯作电压。为使PECL和LVPECL接⼝标准能与Pericom公司的LVDS器件进⾏连接，采⽤电阻分压器在不同电压之间切换。图3：PECL到LVDS的接⼝电路。R1||(R2＋R3)＝Z图1所⽰的接⼝电路采⽤由电阻R1、R2和R3组成的电阻分压器。R1、R2与R3的电阻值计算如下：[(R2＋R3)/(R1＋R2＋R3)]＝Va/VccR3/(R1＋R2＋R3)＝Vb/Vcc其中：Va为SEPC或LVPECL的偏置电压Vos，分别为3.6V和2.0V；Vb为LVDS的偏置电压Vos，等于1.2V；Z为线路阻抗，等于50Ω。Vb上的增益G为：G＝R3/(R2＋R3)Vb上的摆幅为：Vbs＝Vas×G图4：LVDS到PECL的接⼝电路。图5：LVPECL到LVDS的接⼝电路。Vas为Va上的摆幅；Vbs为Vb上的摆幅。其中：由于在计算中没有考虑驱动器的输出阻抗，所以在实际应⽤设计中，R1、R2及R3的电阻值与上述计算的结果不⼀样。另外，不同⼚家的驱动器的输出结构和阻抗不⼀样，因此R1、R2及R3的电阻值也是不同的。可以通过三种⽅法算出电阻值。1.经验法图6：LVDS到LVPECL的接⼝电路。图6：LVDS到LVPECL的接⼝电路。利⽤表2列出的电阻参考值，并根据后⾯介绍的⽅法2及⽅法3来调节这些值。接⼝设计者应通过测量Va和Vb上的偏置电压Vos以及摆幅Vpp来验证实际应⽤设计电路。2.仿真⼯具法从⼚家获得驱动器的IBIS模型，并针对R1、R2及R3的电阻值对接⼝电路进⾏仿真。如果IBIS模型和仿真⼯具都很精确，则电路仿真将提供准确的R1、R2及R3的电阻值，然后通过测量实际电路来验证仿真得到的电阻值。图7：采⽤⼆极管的LVDS到LVPECL的接⼝电路。3.实际调节法采⽤图2所⽰的电路调节R1、R2及R3的电阻值。电阻R1a、R2a及R3a⽤来限制调节范围，以避免出现过载电流。当调节电路并⽤⽰波器监视Va与Vb上的信号时，调节VR1、VR2与VR3：a. 对于Pericom公司的LVDS 接收器，Vb上的Vos(在摆幅范围中间的平均电压)应介于0.8V－1.6V之间。有关Va上的Vos，请查阅驱动器参数。b. 对于Pericom公司的接收器，Vb上的摆动范围应介于350mV－550mV之间。有关Va上的摆幅，请参见驱动器规范，Va上的摆幅可能低于驱动器规范以便满⾜Vb上的摆幅要求。c. 电路调节完以后，再测量VR1与R1a，得到R1的电阻值；测量VR2与图8：CML到LVDS的接⼝电路。R2a，得到R2的电阻值；测量VR3与R3a，得到R3的电阻值。d. ⽤较低频率的信号对电路进⾏调节会更加简单，频率最好介于100kHz－10MHz之间，但请确认电路是否在正常频率下⼯作，如果需要的话可再次调节。图9：LVDS到CML的接⼝电路。接⼝电路的限制由于接⼝电路增加了额外电容与电阻⽹络，因此接⼝电路的最⾼⼯作频率将低于器件⼿册上提供的最⾼频率。驱动器与接收器之间的⾛线长度也有限制，⾛线长度取决于频率，当频率为66MHz时，估计最⼤⾛线长度为14英⼨，频率为320MHz时则为2英⼨。⾛线长度是⼀个实际问题且取决于实际设计。为减少寄⽣电容、电感及信号反射以获得更⾼性能，接⼝电路中器件之间的⾛线应尽量短，越短越好。接⼝电路使⽤的电容、电阻以及⼆极管必须为短引脚的⾼速器件，⽽且最好采⽤芯⽚型封装。图10：RS-422到LVDS的接⼝电路。参考接⼝电路图3⾄图12给出了LVDS与PECL、LVPECL、CML、RS-422及单端器件之间的接⼝电路，它们的调节⽅法以及电路限制如前所述。图11：单端信号到LVDS的接⼝电路。1. LVDS⾄PECL在图4所⽰的LVDS到PECL的接⼝电路⾥，PECL接收器没有内部上拉电阻。该电路中的电阻值仅适⽤于Pericom公司的LVDS驱动器。由于采⽤交流耦合，这个接⼝只能通过交流信号，因此从驱动器传输到接收器的信号必须适合交流耦合。当电容C1与C2为0.1uf时，任何信号状态转换(由⾼⾄低或由低⾄⾼)之间的最⼤时间间隔为500ns。2. LVDS到LVPECL图12：5V单端信号到LVDS的接⼝电路。在图6所⽰的LVDS到LVPECL的接⼝电路⾥，电阻值也仅适⽤于Pericom公司的LVDS驱动器，这⾥的LVPECL接收器没有内部上拉电阻。图7中，⼆极管D1、D2、D3和D4在Va与Vb之间产⽣0.7V的电压差，且其摆幅衰减低于图6电路中的摆幅衰减。这个电路应采⽤正向压降为0.7V的⾼速⼆极管，芯⽚型⼆极管最好。电路中的电阻值适⽤于Pericom公司的LVDS驱动器，LVPECL接收器没有上拉电阻。3. CML到LVDS表1：LVDS、PECL、LVPECL、CML和RS-422接⼝的电压规范。图8接⼝电路采⽤交流耦合，只能通过交流信号，因此从驱动器传输到接收器的信号必须适合交流耦合。当电容C1与C2为0.1uf时，任何信号状态转换(由⾼⾄低或由低⾄⾼)之间的最⼤时间间隔为500ns。图9电路中的电阻值适⽤于Pericom公司的LVDS驱动器，CML接收器带有50Ω的内部上拉电阻。由于采⽤交流耦合，故它仅能通过交流信号，因此从驱动器传输⾄接收器的信号必须适合交流耦合。当电容C1与C2值为0.1uf时，任何信号状态转换(由⾼⾄低或由低⾄⾼)之间的最⼤时间间隔为500ns。4. 单端信号到LVDS当单端CMOS驱动器与Pericom公司的LVDS接收器连接时，可采⽤图11中的电路以及表3中的参数，同时使由R_out和R_termination构成的输出阻抗与50 Ω的⾛线阻抗相匹配，即：R_out＋R_termination＝Z＝50Ω表2：R1、R2和R3的参考值。例如，如果驱动器的输出阻抗为20Ω，则应该采⽤30Ω的R_termination，于是有：20Ω＋30Ω＝50Ω在图12中，根据Vb上的信号质量，R_termination的阻值介于0－22Ω之间。如果Vb上有过冲和下冲，则增加R_termination的阻值；如果Vb上的信号边沿有衰减，则减⼩R_termination的阻值。表3：适合Pericom公本⽂⼩结司接收器的R1、R2和Va值。本⽂提供了⼏个典型的参考电路，可以很⽅便地将不同接⼝标准与Pericom公司的LVDS器件进⾏连接。由于各⼚商提供的驱动器不同，所以本⽂提供的所有电路需要由设计者在实际应⽤前进⾏验证。Pericom公司提供多种LVDS驱动器、接收器及差分时钟分配器件，并将对采⽤Pericom产品的接⼝设计提供⽀持。作者：Scott WuPericom半导体公司相关信息* 什么是LVDS?LVDS即低压差分信号传输(Low Voltage Differential Signal) ，是⼀种满⾜当今⾼性能数据传输应⽤的新型技术。与其它竞争技术相⽐，LVDS在提供⾼数据速率时的功耗要⼩得多，采⽤LVDS技术的产品数据速率可以从数百Mbps到2Gbps以上。它已经⼴泛应⽤在许多要求速度与低功耗的应⽤领域。