Verilog实现的4位超前进位加法器

Verilog实现的4位超前进位加法器。

经过modelsim验证正确可用，在DC下综合成功 //文件名：add_4.v //模块名：add_4 //

module add_4 ( input [3:0]a, input [3:0]b, input cin, output [3:0] s, output co );

wire [3:0]c_tmp; wire [3:0]g; wire [3:0]p; assign co = c_tmp[3];

assign g[0] = a[0] & b[0], g[1] = a[1] & b[1], g[2] = a[2] & b[2], g[3] = a[3] & b[3];

assign p[0] = a[0] | b[0], p[1] = a[1] | b[1], p[2] = a[2] | b[2], p[3] = a[3] | b[3];

assign c_tmp[0] = g[0] | ( p[0] & cin ),

c_tmp[1] = g[1] | ( p[1] & g[0]) | ( p[1] & p[0] & cin),

c_tmp[2] = g[2] | ( p[2] & g[1]) | ( p[2] & p[1] & g[0]) | ( p[2] & p[1] & p[0] & cin),

c_tmp[3] = g[3] | ( p[3] & g[2]) | ( p[3] & p[2] & g[1]) | ( p[3] & p[2] & p[1] & g[0]) | ( p[3] & p[2] & p[1] & p[0] & cin);

assign s[3:0] = a[3:0] ^ b[3:0] ^{c_tmp[2:0],cin}; endmodule