MC74HC574AOctal3-StateNoninvertingDFlip-FlopHigh–Performance Silicon–Gate CMOSThe MC74HC574A is identical in pinout to the LS574. The deviceinputs are compatible with standard CMOS outputs; with pullupresistors, they are compatible with LSTTL outputs.Data meeting the setup time is clocked to the outputs with the risingedge of the Clock. The Output Enable input does not affect the statesof the flip–flops, but when Output Enable is high, all device outputsare forced to the high–impedance state. Thus, data may be stored evenwhen the outputs are not enabled.The HC574A is identical in function to the HC374A but has theflip–flop inputs on the opposite side of the package from the outputs tofacilitate PC board layout.http://onsemi.comMARKINGDIAGRAMS20PDIP–20N SUFFIXCASE 7381MC74HC574ANAWLYYWW12020••••••Output Drive Capability: 15 LSTTL LoadsOutputs Directly Interface to CMOS, NMOS and TTLOperating Voltage Range: 2.0 to 6.0 VLow Input Current: 1.0 µAIn Compliance with the Requirements Defined by JEDEC StandardNo. 7AChip Complexity: 266 FETs or 66.5 Equivalent Gates201SOIC WIDE–20DW SUFFIXCASE 751D1AWLYYWWHC574AAWLYYWW= Assembly Location= Wafer Lot= Year= Work WeekORDERING INFORMATIONDeviceMC74HC574ANMC74HC574ADWMC74HC574ADWR2PackagePDIP–20SOIC–WIDESOIC–WIDEShipping1440 / Box38 / Rail1000 / Reel© Semiconductor Components Industries, LLC, 20001March, 2000 – Rev. 8Publication Order Number:MC74HC574A/DMC74HC574ALOGIC DIAGRAMD0D1D2DATAINPUTSD3D4D5D6D7CLOCKOUTPUT ENABLE23456789111PIN 20 = VCCPIN 10 = GND1918171615141312Q0Q1Q2Q3Q4Q5Q6Q7NON–INVERTINGOUTPUTSPIN ASSIGNMENTOUTPUTENABLED0D1D2D3D4D5D6D7GND1234567891020191817161514131211VCCQ0Q1Q2Q3Q4Q5Q6Q7CLOCKFUNCTION TABLEInputsOELLLHClockDHLXXOutputQHLNo ChangeZL,H,XX = Don’t CareZ = High ImpedanceDesign CriteriaInternal Gate Count*Internal Gate Propagation DelayInternal Gate Power DissipationSpeed Power ProductValue66.51.55.0UnitseansµWpJ0.0075*Equivalent to a two–input NAND gate.http://onsemi.com2MC74HC574AMAXIMUM RATINGS*SymbolVCCVinParameterValueUnitVVVmAmAmAmW_C_CDC Supply Voltage (Referenced to GND)DC Input Voltage (Referenced to GND)DC Output Voltage (Referenced to GND)DC Input Current, per PinDC Output Current, per PinDC Supply Current, VCC and GND PinsPower Dissipation in Still Air,Storage TemperatureLead Temperature, 1 mm from Case for 10 Seconds(Plastic DIP or SOIC Package)– 0.5 to + 7.0– 0.5 to VCC + 0.5– 0.5 to VCC + 0.5±20±35±75750500VoutIinIoutICCPDPlastic DIP†SOIC Package†TstgTL– 65 to + 150260This device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high–impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND v (Vin or Vout) v VCC.Unused inputs must always betied to an appropriate logic voltagelevel (e.g., either GND or VCC).Unused outputs must be left open.*Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the Recommended Operating Conditions.†Derating—Plastic DIP: –10 mW/_C from 65_ to 125_CSOIC Package: –7 mW/_C from 65_ to 125_CFor high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).RECOMMENDED OPERATING CONDITIONSSymbolVCCParameterMin2.00Max6.0UnitVV_CnsDC Supply Voltage (Referenced to GND)DC Input Voltage, Output Voltage (Referenced to GND)Operating Temperature, All Package TypesInput Rise and Fall Time(Figure 1)VCC = 2.0 VVCC = 4.5 VVCC = 6.0 VVin, VoutTAVCC– 55000+ 1251000500400tr, tfDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)Guaranteed Limitv 85_C1.52.13.154.20.50.91.351.81.94.45.9SymbolVIHParameterTest ConditionsVCCV2.03.04.56.02.03.04.56.02.04.56.03.04.56.02.04.56.03.04.56.06.0– 55 to25_C1.52.13.154.20.50.91.351.81.94.45.9v 125_C1.52.13.154.20.50.91.351.81.94.45.92.23.75.20.10.10.10.40.40.4UnitVMinimum High–Level InputVoltageVout = VCC – 0.1 V|Iout| v 20 µAVILMaximum Low–Level InputVoltageVout = 0.1 V|Iout| v 20 µAVVOHMinimum High–Level OutputVoltageVin = VIH|Iout| v 20 µAVin = VIHV|Iout| v 2.4 mA|Iout| v 6.0 mA|Iout| v 7.8 mA2.483.985.480.10.10.12.343.845.340.10.10.1VOLMaximum Low–Level OutputVoltageVin = VIL|Iout| v 20 µAVin = VILV|Iout| v 2.4 mA|Iout| v 6.0 mA|Iout| v 7.8 mA0.260.260.260.330.330.33IinMaximum Input LeakageCurrentVin = VCC or GND±0.1±1.0±1.0µAhttp://onsemi.com3MC74HC574ADC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)Guaranteed Limitv 85_C±5.0SymbolIOZParameterMaximum Three–StateLeakage CurrentTest ConditionsOutput in High–Impedance StateVin = VIL or VIHVout = VCC or GNDVin = VCC or GNDIout = 0 µAVCCV6.0– 55 to25_C±0.5v 125_C±10UnitµAICCMaximum Quiescent SupplyCurrent (per Package)6.04.040160µANOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book(DL129/D).DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)Guaranteed LimitSymbolIOZParameterTest ConditionsVCCV6.0– 55 to25_C±0.5v 85_C±5.0v 125_C±10UnitµAMaximum Three–StateLeakage CurrentOutput in High–Impedance StateVin = VIL or VIHVout = VCC or GNDVin = VCC or GND|Iout| = 0 µAICCMaximum Quiescent SupplyCurrent (per Package)6.04.040160µAAC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)Guaranteed LimitSymbolfmaxParameterVCCV2.03.04.56.02.03.04.56.02.03.04.56.02.03.04.56 02.03.04.56.0– 55 to25_C6.0153035v 85_C4.8102428v 125_C4.08.02024UnitMaximum Clock Frequency (50% Duty Cycle)(Figures 1 and 4)MHztPLH,tPHLMaximum Propagation Delay, Clock to Q(Figures 1 and 4)16010532271501003026140902824602712101015200145403419012538331751203530753215131015240190484122515045382101404236903618151015nstPLZ,tPHZMaximum Propagation Delay, Output Enable to Q(Figures 2 and 5)nstPZL,tPZHMaximum Propagation Delay, Output Enable to Q(Figures 2 and 5)nstTLH,tTHLMaximum Output Transition Time, any Output(Figures 1 and 4)nsCinCoutMaximum Input CapacitanceMaximum Three–State Output Capacitance, Output in High–ImpedanceStatepFpFNOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ONSemiconductor High–Speed CMOS Data Book (DL129/D).Typical @ 25°C, VCC = 5.0 VCPDPower Dissipation Capacitance (Per Enabled Output)*24pF*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of theON Semiconductor High–Speed CMOS Data Book (DL129/D).http://onsemi.com4MC74HC574ATIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)Guaranteed Limitv 85_CMin65501311MaxSymboltsuParameterMinimum Setup Time, Data to ClockFig.3VCCVolts2.03.04.66.02.03.04.56.02.03.04.56.02.03.04.56.0– 55 to 25_CMin5040109.0Maxv 125_CMin75601513MaxUnitnsthMinimum Hold Time, Clock to Data35.05.05.05.0756015135.05.05.05.0958019165.05.05.05.0nstwMinimum Pulse Width, Clock1110902219nstr, tfMaximum Input Rise and Fall Times1100080050040010008005004001000800500400nshttp://onsemi.com5MC74HC574ASWITCHING WAVEFORMStrCLOCK90%50%10%tw1/fmaxtPLHQ90%50%10%tTLHtTHLtPHLQtfVCC1.3 VGNDtPZL1.3 VtPZHQtPHZ10%90%tPLZGNDHIGHIMPEDANCEVOLVOHHIGHIMPEDANCE3.0 VFigure 1. Figure 2. VALIDDATA50%tsuCLOCKthVCC50%GNDD13VCCGNDD02EXPANDED LOGIC DIAGRAMCQDCQDCQDCQDCQDCQDCQDCQD11119Q018Q1Figure 3. D2TEST POINTD3OUTPUTDEVICEUNDERTESTCL*D4417Q2516Q3615Q4D5*Includes all probe and jig capacitance714Q5Figure 4. D6813Q6TEST POINTOUTPUTDEVICEUNDERTEST1 kΩCONNECT TO VCC WHENTESTING tPLZ AND tPZL.CONNECT TO GND WHENTESTING tPHZ AND tPZH.D7912Q7CLOCKOUTPUT ENABLECL**Includes all probe and jig capacitanceFigure 5. Test Circuithttp://onsemi.com6MC74HC574APACKAGE DIMENSIONSPDIP–20N SUFFIXPLASTIC DIP PACKAGECASE 738–03ISSUE E11–A–20B110CLNOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLDFLASH.DIMABCDEFGJKLMNINCHESMILLIMETERSMINMAXMINMAX1.0101.07025.6627.170.2400.2606.106.600.1500.1803.814.570.0150.0220.390.550.050 BSC1.27 BSC0.0500.0701.271.770.100 BSC2.54 BSC0.0080.0150.210.380.1100.1402.803.550.300 BSC7.62 BSC0 15 0 15 ____0.0200.0400.511.01–T–SEATINGPLANEKMEGFD20 PLNJ0.25 (0.010)M20 PL0.25 (0.010)TAMMTBMSO–20DW SUFFIXCASE 751D–05ISSUE FDA11X 45_qNOTES:1.DIMENSIONS ARE IN MILLIMETERS.2.INTERPRET DIMENSIONS AND TOLERANCESPER ASME Y14.5M, 1994.3.DIMENSIONS D AND E DO NOT INCLUDE MOLDPROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5.DIMENSION B DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE PROTRUSION SHALLBE 0.13 TOTAL IN EXCESS OF B DIMENSION ATMAXIMUM MATERIAL CONDITION.MILLIMETERSMINMAX2.352.650.100.250.350.490.230.3212.6512.957.407.601.27 BSC10.0510.550.250.750.500.900 7 __HMBM2010X0.25E110h20XB0.25MBTASBSAeSEATINGPLANE18XA1TCDIMAA1BCDEeHhLqhttp://onsemi.com7LMC74HC574A
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