Octal 3-State NoninvertingD Flip-Flop
High–Performance Silicon–Gate CMOS
The MC74HC574A is identical in pinout to the LS574. The deviceinputs are compatible with standard CMOS outputs; with pull–upresistors, they are compatible with LSTTL outputs.
Data meeting the set–up time is clocked to the outputs with therising edge of the Clock. The Output Enable input does not affect thestates of the flip–flops but when Output Enable is high, all deviceoutputs are forced to the high–impedance state. Thus, data may bestored even when the outputs are not enabled.
The HC574A is identical in function to the HC374A but has theflip–flop inputs on the opposite side of the package from the outputs tofacilitate PC board layout.
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MARKINGDIAGRAMS
20
1
MC74HC574ANAWLYYWW
••••••
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTLOperating Voltage Range: 2.0 to 6.0 VLow Input Current: 1.0 mA
In Compliance with the Requirements Defined by JEDEC StandardNo. 7A
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
PDIP–20N SUFFIXCASE 783
20
1
SO–20DW SUFFIXCASE 751D
HC574AAWLYYWW
201
TSSOP–20DT SUFFIXCASE 948E
HC574AALYW
A= Assembly LocationL, WL= Wafer LotY, YY= Year
W, WW= Work Week
ORDERING INFORMATION
Device
MC74HC574ANMC74HC574ADWMC74HC574ADWR2MC74HC574ADTMC74HC574ADTR2
PackagePDIP–20SOIC–WIDESOIC–WIDETSSOP–20TSSOP–20
Shipping1440/Box38/Rail1000/Reel75/Rail2500/Reel
© Semiconductor Components Industries, LLC, 20011May, 2001 – Rev. 9
Publication Order Number:
MC74HC574A/D
MC74HC574A
OUTPUTENABLE
D0
D1D2D3D4D5D6D7GND
1234567891020191817161514131211VCCQ0Q1Q2Q3Q4Q5Q6Q7CLOCK
OELLLH
FUNCTION TABLE
InputsClock
DHLXX
OutputQHL
No Change
Z
L,H,X
X = Don’t Care
Z = High Impedance
Figure 1. Pin Assignment
D0D1D2
DATAINPUTS
D3D4D5D6D7CLOCK
OUTPUT ENABLE
234567891111918171615141312Q0Q1Q2Q3Q4Q5Q6Q7NONINVERTINGOUTPUTS
PIN 20 = VCCPIN 10 = GND
Figure 2. Logic Diagram
Design CriteriaInternal Gate Count*Internal Gate Propagation DelayInternal Gate Power DissipationSpeed Power Product*Equivalent to a two–input NAND gate.Value66.51.55.0Unitsea.nsmWpJ0.0075http://onsemi.com
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MC74HC574A
MAXIMUM RATINGS (Note 1)SymbolVCCVIVOIIKIOKIOICCIGNDTSTGTLTJqJADC Supply VoltageDC Input VoltageDC Output VoltageDC Input Diode CurrentDC Output Diode CurrentDC Output Sink CurrentDC Supply Current per Supply PinDC Ground Current per Ground PinStorage Temperature RangeLead Temperature, 1 mm from Case for 10 SecondsJunction Temperature under BiasThermal ResistancePDIPSOICTSSOPPDIPSOICTSSOP(Note 2)ParameterValue*0.5 to )7.0*0.5 to VCC )0.5*0.5 to VCC )0.5$20$35$35$75$75*65 to )150260)1506796128750500450Level 1Oxygen Index: 30% – 35%Human Body Model (Note 3)Machine Model (Note 4)Charged Device Model (Note 5)Above VCC and Below GND at 85_C (Note 6)UL–94–VO (0.125 in)>4000>300>1000$300VUnitVVVmAmAmAmAmA_C_C_C_C/WPDPower Dissipation in Still Air at 85_CmWMSLFRVESDMoisture SensitivityFlammability RatingESD Withstand VoltageILatch–UpLatch–Up PerformancemA1.Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to theseconditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum–ratedconditions is not implied.
2.IO absolute maximum rating must be observed.3.Tested to EIA/JESD22–A114–A.4.Tested to EIA/JESD22–A115–A.5.Tested to JESD22–C101–A.6.Tested to EIA/JESD78.
7.For high frequency or heavy load considerations, see the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
SymbolVCCVI, VOTAtr, tfDC Supply VoltageDC Input Voltage, Output VoltageOperating Temperature, All Package TypesInput Rise and Fall Time (Figure 3)VCC = 2.0 VVCC = 4.5 VVCC = 6.0 VParameter(Referenced to GND)(Referenced to GND)Min2.00*55000Max6.0VCC)1251000500400UnitVV_Cns8.Unused inputs may not be left open. All inputs must be tied to a high– or low–logic input voltage level.
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MC74HC574A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
SymbolVIHParameterMinimum High–Level InputVoltageTest ConditionsVout = VCC – 0.1 V|Iout| v 20 mAVCCV2.03.04.56.02.03.04.56.02.04.56.03.04.56.02.04.56.03.04.56.06.06.0Guaranteed Limit*55 to 25_C1.52.13.154.20.50.91.351.81.94.45.9v85_C1.52.13.154.20.50.91.351.81.94.45.9v125_C1.52.13.154.20.50.91.351.81.94.45.92.23.75.20.10.10.10.40.40.4UnitVVILMaximum Low–Level InputVoltageVout = 0.1 V|Iout| v 20 mAVVOHMinimum High–Level OutputVoltageMinimum High–Level OutputVoltageVin = VIH|Iout| v 20 mAVin = VIHVVOH|Iout| v 2.4 mA|Iout| v 6.0 mA|Iout| v 7.8 mA2.483.985.480.10.10.12.343.845.340.10.10.1VVOLMaximum Low–Level OutputVoltageVin = VIL|Iout| v 20 mAVin = VILV|Iout| v 2.4 mA|Iout| v 6.0 mA|Iout| v 7.8 mA0.260.260.260.330.330.33IinMaximum Input LeakageCurrentMaximum Three–StateLeakage CurrentVin = VCC or GND$0.1$0.5$1.0$5.0$1.0$10mAmAIOZOutput in High–Impedance StateVin = VIL or VIHVout = VCC or GNDVin = VCC or GNDIout = 0 mAICCMaximum Quiescent SupplyCurrent (per Package)6.04.040160mA9.Information on typical parametric values can be found in the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
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4
MC74HC574A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns)
SymbolfmaxParameterMaximum Clock Frequency (50% Duty Cycle)(Figures 3 and 6)VCCV2.03.04.56.02.03.04.56.02.03.04.56.02.03.04.56 02.03.04.56.0Guaranteed Limit*55 to 25_C6.0153035v85_C4.8102428v125_C4.08.02024UnitMHztPLH,tPHLMaximum Propagation Delay, Clock to Q(Figures 3 and 6)16010532271501003026140902824602712101015200145403419012538331751203530753215131015240190484122515045382101404236903618151015nstPLZ,tPHZMaximum Propagation Delay, Output Enable to Q(Figures 4 and 7)nstPZL,tPZHMaximum Propagation Delay, Output Enable to Q(Figures 4 and 7)nstTLH,tTHLMaximum Output Transition Time, any Output(Figures 3 and 6)nsCinCoutMaximum Input CapacitanceMaximum Three–State Output Capacitance, Output in High–ImpedanceStatepFpF10.For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 VCPDPower Dissipation Capacitance (Per Enabled Output)*24pF*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see the ONSemiconductor High–Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (CL = 50 pF; Input tr = tf = 6.0 ns)
Guaranteed LimitVCCSymboltsu– 55 to 25_CMin5040109.0Maxv 85_CMin65501311Maxv 125_CMin75601513MaxUnitnsParameterMinimum Setup Time, Data to ClockFigure5Volts2.03.04.66.02.03.04.56.02.03.04.56.02.03.04.56.0thMinimum Hold Time, Clock to Data55.05.05.05.0756015135.05.05.05.0958019165.05.05.05.0nstwMinimum Pulse Width, Clock3110902219nstr, tfMaximum Input Rise and Fall Times3100080050040010008005004001000800500400nshttp://onsemi.com
5
MC74HC574A
SWITCHING WAVEFORMStrCLOCK90%50%10%tw1/fmaxtPLHQ90%50%10%tTLHtTHLtPHLtfVCCGND1.3 VGND
tPZLQ1.3 VtPZHQtPHZ10%90%tPLZHIGH
IMPEDANCEVOLVOH
HIGH
IMPEDANCE3.0 V
Figure 3. Figure 4.
TEST POINT
VALIDDATA50%tsuCLOCKthVCC
50%GNDVCCGND
DEVICEUNDERTESTOUTPUTCL*
*Includes all probe and jig capacitance.
Figure 5. Figure 6.
CQDCQDCQDCQDCQDCQDCQDCQD11119D0
2Q0
D1
318Q1
D2
417Q2
TEST POINTOUTPUTDEVICEUNDERTEST1 kΩCONNECT TO VCC WHENTESTING tPLZ AND tPZL.CONNECT TO GND WHENTESTING tPHZ AND tPZH.
D3
516Q3
D4
615Q4
CL*D5
*Includes all probe and jig capacitance.
D6
714Q5
813Q6
Figure 7. Test Circuit
D7
912Q7
CLOCKOUTPUT ENABLEFigure 8. Expanded Logic Diagram
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6
MC74HC574A
PACKAGE DIMENSIONS
PDIP–20N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03ISSUE E
–A–20111NOTES:
1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.
2.CONTROLLING DIMENSION: INCH.
3.DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.
4.DIMENSION B DOES NOT INCLUDE MOLDFLASH.
DIMABCDEFGJKLMNINCHESMINMAX1.0101.0700.2400.2600.1500.1800.0150.0220.050 BSC0.0500.0700.100 BSC0.0080.0150.1100.1400.300 BSC0 _15 _0.0200.040MILLIMETERSMINMAX25.6627.176.106.603.814.570.390.551.27 BSC1.271.772.54 BSC0.210.382.803.557.62 BSC0 _15 _0.511.01B10CL–T–SEATINGPLANEKMEGFD20 PLNJ0.25 (0.010)M20 PL0.25 (0.010)TAMMTBMSO–20DW SUFFIXCASE 751D–05
ISSUE F
DA11X 45_qNOTES:1.DIMENSIONS ARE IN MILLIMETERS.2.INTERPRET DIMENSIONS AND TOLERANCESPER ASME Y14.5M, 1994.3.DIMENSIONS D AND E DO NOT INCLUDE MOLDPROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.5.DIMENSION B DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE PROTRUSION SHALLBE 0.13 TOTAL IN EXCESS OF B DIMENSION ATMAXIMUM MATERIAL CONDITION.DIMAA1BCDEeHhLqMILLIMETERSMINMAX2.352.650.100.250.350.490.230.3212.6512.957.407.601.27 BSC10.0510.550.250.750.500.900 7 __HMBM2010X0.25E11020XB0.25MBTASBSAeSEATINGPLANEh18XA1TChttp://onsemi.com
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LMC74HC574A
PACKAGE DIMENSIONS
TSSOP–20DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X REFK0.15 (0.006)TUS0.10 (0.004)MTUSVS2XL/22011KK1LPIN 1IDENT110B–U–JJ1SECTION N–N0.25 (0.010)MN0.15 (0.006)TUSOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.
2.CONTROLLING DIMENSION: MILLIMETER.
3.DIMENSION A DOES NOT INCLUDE MOLD FLASH,PROTRUSIONS OR GATE BURRS. MOLD FLASHOR GATE BURRS SHALL NOT EXCEED 0.15(0.006) PER SIDE.
4.DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH ORPROTRUSION SHALL NOT EXCEED 0.25 (0.010)PER SIDE.
5.DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL INEXCESS OF THE K DIMENSION AT MAXIMUMMATERIAL CONDITION.
6.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.
7.DIMENSION A AND B ARE TO BE DETERMINEDAT DATUM PLANE -W-.
DIMABCDFGHJJ1KK1LMMILLIMETERSINCHESMINMAXMINMAX6.406.600.2520.2604.304.500.1690.177---1.20---0.0470.050.150.0020.0060.500.750.0200.0300.65 BSC0.026 BSC0.270.370.0110.0150.090.200.0040.0080.090.160.0040.0060.190.300.0070.0120.190.250.0070.0106.40 BSC0.252 BSC0 8 0 8 ____A–V–NFDETAIL ECD0.100 (0.004)–T–SEATINGPLANE–W–GHDETAIL EN
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