专利名称：Apparatus for reducing leakage in global
bit-line architectures
发明人：Anthony Correale, Jr.,Rahul K. Nadkarni申请号：US11950459申请日：20071205公开号：US07619923B2公开日：20091117
专利附图：
摘要：A circuit for reducing current leakage in hierarchical bit-line architecturesincludes a sense amplifier having transistors, the sense amplifier coupled to bit-lines ofcells in a memory array, the sense amplifier configured for detecting stored data from
one of the cells; an output latch having transistors, the output latch selectively coupledto a global bit-line of the sense amplifier having a logical state, the output latchconfigured for selectively reading out stored data from one of the cells through theglobal bit-line; and a transmission gating device coupled between the sense amplifier andthe output latch for selectively coupling the sense amplifier to the output latch
correspondingly eliminating a first leakage path and forming a second leakage path, thefirst leakage path being between the sense amplifier and the output latch, the secondleakage path formed within the sense amplifier.
申请人：Anthony Correale, Jr.,Rahul K. Nadkarni
地址：Raleigh NC US,Greenville IN US
国籍：US,US
代理机构：Cantor Colburn LLP
代理人：Mark McBurney
更多信息请下载全文后查看
因篇幅问题不能全部显示，请点此查看更多更全内容