1.动态扫描显示程序： library ieee;
use ieee.std_logic_1164.all;
entity dtsm_xs is
port(clk:in std_logic;
B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1:in std_logic_vector(3 downto 0); x:out std_logic_vector(6 downto 0);
led_select: out std_logic_vector(13 downto 0)); end;
architecture behave of dtsm_xs is
signal bcd_in: std_logic_vector(3 downto 0); signal cnt2: integer range 0 to 13; begin
p1:process(clk) begin
if clk'event and clk='1' then if cnt2>=13 then cnt2<=0; else
cnt2<=cnt2+1; end if; end if;
end process;
p2:process(cnt2,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1) begin
case cnt2 is
when 0=>led_select<=\"11111111111110\";bcd_in<=B1; when 1=>led_select<=\"11111111111101\";bcd_in<=B2; when 2=>led_select<=\"11111111111011\";bcd_in<=B3; when 3=>led_select<=\"11111111110111\";bcd_in<=B4; when 4=>led_select<=\"11111111101111\";bcd_in<=B5; when 5=>led_select<=\"11111111011111\";bcd_in<=B6; when 6=>led_select<=\"11111110111111\";bcd_in<=B7; when 7=>led_select<=\"11111101111111\";bcd_in<=B8; when 8=>led_select<=\"11111011111111\";bcd_in<=B9; when 9=>led_select<=\"11110111111111\";bcd_in<=B10; when 10=>led_select<=\"11101111111111\";bcd_in<=B11; when 11=>led_select<=\"11011111111111\";bcd_in<=B12; when 12=>led_select<=\"10111111111111\";bcd_in<=B13; when 13=>led_select<=\"01111111111111\";bcd_in<=B14; end case; end process; p3:process(bcd_in)
begin
case bcd_in is
when \"0000\"=>x<=\"1111110\"; when \"0001\"=>x<=\"0110000\"; when \"0010\"=>x<=\"1101101\"; when \"0011\"=>x<=\"1111001\"; when \"0100\"=>x<=\"0110011\"; when \"0101\"=>x<=\"1011011\"; when \"0110\"=>x<=\"1011111\"; when \"0111\"=>x<=\"1110000\"; when \"1000\"=>x<=\"1111111\"; when \"1001\"=>x<=\"1111011\"; when others=>x<=\"0000000\"; end case; end process; end;
2.分频器设计程序 library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity divider_1m is port(clk: in std_logic;
clk_1Hz: out std_logic;
clk_500Hz:buffer std_logic); end divider_1m;
architecture rtl of divider_1m is signal cnt1:integer range 0 to 1999; signal cnt2:integer range 0 to 499; begin
p1:process(clk) begin
if clk'event and clk='1' then if cnt1=cnt1'high then cnt1<=0; else
cnt1<=cnt1+1; end if; end if; end process;
p2:process(clk,cnt1) begin
if clk'event and clk='1' then
if cnt1>=999 then clk_500Hz<='1'; else
clk_500Hz<='0'; end if; end if;
end process;
p3:process(clk_500Hz) begin
if clk_500Hz'event and clk_500Hz='1' then if cnt2=cnt2'high then cnt2<=0; else
cnt2<=cnt2+1; end if; end if; end process;
p4:process(clk_500Hz,cnt2) begin
if clk_500Hz'event and clk_500Hz='1' then if cnt2>=249 then clk_1Hz<='1'; else
clk_1Hz<='0'; end if; end if;
end process; end rtl;
3. 8位移位寄存器 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG8 IS
PORT(LOAD,CLR,DIRE,EN,CLK:IN STD_LOGIC;
DATA :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT :BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0)); END REG8;
ARCHITECTURE A OF REG8 IS BEGIN
PROCESS(LOAD,CLR,DIRE,EN,CLK) VARIABLE X:STD_LOGIC; BEGIN
IF LOAD='1' THEN DOUT<=DATA;
ELSIF CLR='1' THEN DOUT<=\"00000000\";
ELSIF EN='1' THEN DOUT<=DOUT;
ELSIF CLK'EVENT AND CLK='1' THEN IF DIRE='1'THEN X:=DOUT(7);
DOUT(7 DOWNTO 1)<=DOUT(6 DOWNTO 0); DOUT(0)<=X; ELSE
X:=DOUT(0);
DOUT(6 DOWNTO 0)<=DOUT(7 DOWNTO 1); DOUT(7)<=X; END IF; END IF; END IF;
END PROCESS; END A;
4.BCD计数器设计(任意进制)
LIBRARY ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;
ENTITY cnt365 IS
PORT(clk,reset:IN STD_LOGIC; daout:out std_logic_vector (9 downto 0)); END;
ARCHITECTURE fun OF cnt365 IS
SIGNAL count: STD_LOGIC_VECTOR(9 downto 0);
BEGIN daout <= count; p1:process(clk,reset) begin if (reset='1') then count <= \"0000000000\"; elsif (clk'event and clk='1') then
if count(9 downto 0)=\"1101100100\"then count(9 downto 0)<=\"0000000000\"; elsif count(7 downto 0)=\"10011001\" then count<=count + \"01100111\"; elsif count(3 downto 0)=\"1001\" then count<=count + \"0111\";
else count <= count + 1; end if; end if;
end process p1; END fun;
5.基于状态机的计数器设计 library ieee;
use ieee.std_logic_1164.all;
entity statemachine_counter is port(clr,clk: in std_logic;
q:out std_logic_vector(2 downto 0)); end;
architecture a of statemachine_counter is type state_type is (s0,s1,s2,s3,s4,s5,s6); signal present_state,next_state: state_type;
begin
p1:process(clk,clr) begin
if clr='1' then
present_state<=s0;
elsif clk'event and clk='1' then present_state<=next_state; end if;
end process p1;
p2:process(clk,present_state) begin
case present_state is
when s0=>next_state<=s1; when s1=>next_state<=s2; when s2=>next_state<=s3; when s3=>next_state<=s4; when s4=>next_state<=s5; when s5=>next_state<=s6; when s6=>next_state<=s0; end case; end process p2;
p3:process(clr,present_state) begin
if clr='1' then q<=\"000\"; else
case present_state is when s0=>q<=\"000\"; when s1=>q<=\"001\"; when s2=>q<=\"010\"; when s3=>q<=\"011\"; when s4=>q<=\"100\"; when s5=>q<=\"101\"; when s6=>q<=\"110\"; end case; end if;
end process p3; end a;
LED灯控制
--设计一个循环彩灯控制器，该控制器控制红，绿，黄三个发光二极管循环发亮 --要求红发光管亮2秒，绿亮3秒，黄亮1秒。 library ieee;
use ieee.std_logic_1164.all;
entity asm_led is
port(clr,clk: in std_logic;
led1,led2,led3:out std_logic); end;
architecture a of asm_led is
type state_type is (s0,s1,s2,s3,s4,s5,s6); signal present_state,next_state: state_type;
begin
p1:process(clk,clr) begin
if clr='1' then
present_state<=s0;
elsif clk'event and clk='1' then present_state<=next_state; end if;
end process p1;
p2:process(clk,present_state) begin
case present_state is
when s0=>next_state<=s1;
when s1=>next_state<=s2; when s2=>next_state<=s3; when s3=>next_state<=s4; when s4=>next_state<=s5; when s5=>next_state<=s6; when s6=>next_state<=s1;
end case; end process p2;
p3:process(clr,present_state) begin
if clr='1' then
led1<='0';led2<='0';led3<='0'; else
case present_state is when s0=>
led1<='0';led2<='0';led3<='0'; when s1=>
led1<='1';led2<='0';led3<='0';--led1(黄色发光管点亮1秒） when s2=>
led1<='0';led2<='1';led3<='0';--led2(红色发光管点亮2秒） when s3=>
led1<='0';led2<='1';led3<='0'; when s4=>
led1<='0';led2<='0';led3<='1';--led3(绿色发光管点亮3秒) when s5=>
led1<='0';led2<='0';led3<='1'; when s6=>
led1<='0';led2<='0';led3<='1'; end case; end if;
end process p3; end a;
6.BCD显示译码器 library ieee;
use ieee.std_logic_1164.all; entity decoder7 is
port(bcd: in std_logic_vector(3 downto 0); dout: out std_logic_vector(6 downto 0)); end decoder7;
architecture rtl of decoder7 is
begin
process(bcd) begin
case bcd is
when b\"0000\"=>dout<=b\"0111111\"; when b\"0001\"=>dout<=b\"0000110\"; when b\"0010\"=>dout<=b\"1011011\"; when b\"0011\"=>dout<=b\"1001111\"; when b\"0100\"=>dout<=b\"1100110\"; when b\"0101\"=>dout<=b\"1101101\"; when b\"0110\"=>dout<=b\"1111101\"; when b\"0111\"=>dout<=b\"0000111\"; when b\"1000\"=>dout<=b\"1111111\"; when b\"1001\"=>dout<=b\"1101111\"; when others=>dout<=\"0000000\"; when others=>null; end case; end process; end rtl;
7.100M频率计设计 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FREQUENCY_TEST IS PORT(FSIN:IN STD_LOGIC; CLK:IN STD_LOGIC;
DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); END FREQUENCY_TEST;
ARCHITECTURE BEHAVE OF FREQUENCY_TEST IS SIGNAL TEST_EN:STD_LOGIC; SIGNAL CLEAR:STD_LOGIC;
SIGNAL DATA:STD_LOGIC_VECTOR(31 DOWNTO 0); BEGIN
PROCESS(CLK) BEGIN
IF CLK'EVENT AND CLK='1' THEN TEST_EN<=NOT TEST_EN; END IF;
END PROCESS;
CLEAR<=NOT CLK AND NOT TEST_EN; PROCESS(FSIN) BEGIN
IF CLEAR='1' THEN
DATA<=\"00000000000000000000000000000000\"; ELSIF FSIN'EVENT AND FSIN='1' THEN
IF DATA(31 DOWNTO 0)=\"10011001100110011001100110011001\" THEN DATA<=DATA+\"01100110011001100110011001100111\";
ELSIF DATA(27 DOWNTO 0)=\"1001100110011001100110011001\" THEN DATA<=DATA+\"0110011001100110011001100111\";
ELSIF DATA(23 DOWNTO 0)=\"100110011001100110011001\" THEN DATA<=DATA+\"011001100110011001100111\";
ELSIF DATA(19 DOWNTO 0)=\"10011001100110011001\" THEN DATA<=DATA+\"01100110011001100111\";
ELSIF DATA(15 DOWNTO 0)=\"1001100110011001\" THEN DATA<=DATA+\"0110011001100111\";
ELSIF DATA(11 DOWNTO 0)=\"100110011001\" THEN DATA<=DATA+\"011001100111\";
ELSIF DATA(7 DOWNTO 0)=\"10011001\" THEN DATA<=DATA+\"01100111\";
ELSIF DATA(3 DOWNTO 0)=\"1001\" THEN DATA<=DATA+\"0111\"; ELSE
DATA<=DATA+'1'; END IF; END IF;
END PROCESS;
PROCESS(TEST_EN,DATA) BEGIN
IF TEST_EN'EVENT AND TEST_EN='0' THEN DOUT<=DATA; END IF; END PROCESS; END BEHAVE;
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