PROGRAMMABLE TIMER
s
s
s
s
s
ss
ss
24 FLIP-FLOP STAGES - COUNTS FROM 20 TO 224
LAST 16 STAGES SELECTABLE BY BCD SELECT CODE
GROUP SELECT INDICATES ONE OR MORE PRIORITY INPUTS
QUIESCENT CURRENT SPECIFIED UP TO 20V
STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS
5V, 10V AND 15V PARAMETRIC RATINGSINPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B \"STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES\"
DIPORDER CODES
PACKAGE
DIP
TUBEHCF4536BEY
DESCRIPTION
HCF4536B is a monolithic integrated circuitfabricated in Metal Oxide Semiconductortechnology available in DIP package.
HCF4536B is a programmable timer consisting of24 ripple-binary counter stages. The salientfeature of this device is its flexibility. The devicecan count from 1 to 224 or the first 8 stages can bebypassed to allow an output, selectable by a 4-bitcode, from any one of the remaining 16 stages. ItPIN CONNECTION
bOelos terP)s(tcudoO -can be driven by an external clock or an RC
oscillator that can be constructed using on-chipcomponents. Input IN1 serves as either theexternal clock input or the input to the on-chip RCoscillator. OUT1 and OUT2 are connectionterminals for the external RC components. Inaddition, an on-chip monostable circuit is providedto allow a variable pulse width output. Varioustiming functions can be achieved usingcombinations of these capabilities. A logic \"1\" onthe 8-BYPASS input enables a bypass of the first8 stages and makes stage 9 the first counter stageof the last 16 stages. Selection of 1 of 16 outputsis accomplished by the decoder and the BCDinputs A, B, C, and D. MONO IN is the timing input
elosbrP tetcudoT & R
)(sOctober 20021/13
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HCF4536B
for the on-chip monostable oscillator. Groundingof the MONO IN terminal through a resistor of 10KΩ or higher, disables the one shot circuit andconnects the decoder directly to the DECODEOUT terminal. A resistor to VDD and a capacitor toground from the MONO IN terminal enables theINPUT EQUIVALENT CIRCUIT
one-shot circuit and controls its pulse width. A fasttest mode is enabled by a logic \"1\" on 8-BYPASS,SET, and RESET. This mode divides the 24-stagecounter into three 8-stage sections to facilitate afast test sequence.
PIN DESCRIPTION
PIN No9, 10, 11, 12
12
15634, 5137148
SYMBOLA, B, C, DSETRESET
NAME AND FUNCTION
FUNCTIONAL DIAGRAM
bOelos terP)s(tcudoO -elosb16
Binary Select Input
Set inputReset Input
Monostable OscillatorTim-MONO IN
ing Input
8Bypass input( bypass
8BYPASS
the first 8 stages)
External Clock Input or
IN1
RC oscillator Input
OUT1, OUT2OutputsDECODE
Decode Out Terminal
OUTCLOCK
Clock Inhibit Input
INHIBITOSC.
Oscillator Inhibit Input
INHIBITVSSNegative Supply Voltage
rP teVDD
tcudo )(sPositive Supply Voltage
2/13
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HCF4536B
TRUTH TABLE
In1SetLLXXXLHX : Don’t CareResetLLLHLLLClock InhLLLLHLLOsc. InhLLLLLXOut1Out2Decode OutNo ChangeAdvance to Next StateHLLLLLLLHHHHLNo ChangeNo ChangeAdvance to Next StateDECODE OUT SELECTION TABLE
DLLLLLLLLHHHHHHHH
CLLLLHHHHLLLLHHHH
BLLHHLLHHLLHHLLHH
ALHLHLHLHLHLHLHLH
NUMBER OF STAGES IN DIVIDER CHAIN8-BYPASS = 0
9101112131415161718192021222324
8-BYPASS = 1
BLOCK DIAGRAM
bOelos terP)s(tcudoO -elosbrP tetcudo1
2345678910111213141516
)(s3/13
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HCF4536B
LOGIC DIAGRAM
bOelos terP)s(tcudoO -elosbrP tetcudo )(s4/13
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HCF4536B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
bOSymbolVDDVIIIPDTopTstg
elos terP)s(tcudoParameter
O -elosbrP tetcudo )(sValue-0.5 to +22-0.5 to VDD + 0.5
± 10200
100-55 to +125-65 to +150
UnitVVmAmWmW°C°C
Supply VoltageDC Input VoltageDC Input Current
Power Dissipation per Package
Power Dissipation per Output TransistorOperating TemperatureStorage Temperature
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
All voltage values are referred to VSS pin voltage.
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HCF4536B
RECOMMENDED OPERATING CONDITIONS
SymbolVDDVITop
Supply VoltageInput Voltage
Operating Temperature
Parameter
Value3 to 200 to VDD-55 to 125
UnitVV°C
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
VI(V)0/50/100/150/200/50/100/155/010/015/0
0.5/4.51/91.5/13.54.5/0.59/113.5/1.52.54.69.513.50.40.51.5VO(V)
|IO|VDD(µA)(V)
5101520510155101551015510155510155101518
TA = 25°CMin.
Typ.0.040.040.040.08
4.959.9514.95
0.050.050.053.5711
Max.51020100
4.959.9514.95Value-40 to 85°CMin.
Max.1503006003000
-55 to 125°CMin.
Max.1503006003000
4.959.9514.95
Unit
IL
Quiescent Current
VOH
High Level Output Voltage
Low Level Output Voltage
High Level Input VoltageLow Level Input VoltageOutput Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current
II
CI
sbOThe Noise Margin for both \"1\" and \"0\" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
eloInput Leakage
Current
Input Capacitance
terP)s(tcudo0/5
0/50/100/150/50/100/150/18
Any InputAny Input
<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1<1
O -elosb-3.2
-1-2.6-6.812.66.8±10-55
rP te3.5711-1.1-0.36-0.9-2.40.360.92.4
0.050.050.05
udo1.534
ct )(sVVV
µA
0.05
0.050.05
3.5711
1.534
-1.1-0.36-0.9-2.40.360.92.4
1.534
V
-1.36-0.44-1.1-3.00.441.13.0
mA
mA
±0.17.5
±1±1µApF
6/13
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HCF4536B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
Test Condition
Symbol
Parameter
VDD (V)
Min.
Value (*)Typ.10.50.352.50.80.641.51150755030012580310.751005040200755020010060310.752.510.63.51.51
Max.210.750.61.2832300150100600250160621.520010080400150100400200120621.5521.6732
µsUnit
tPLH tPHLPropagation Delay Time
(Clock to Q1, 8-Bypass High)
bO5
1015
Propagation Delay Time 5(Clock to Q1, 8-Bypass 10Low)
15
Propagation Delay Time 5(Clock to Q16)10
15
Propagation Delay Time 5(Qn to Qn+1)10
15
Propagation Delay Time 5tPLH
1015
Reset to Qn 5tPHL
10155tTHL tTLHTransition Time
1015
Pulse Width Clock 5tW
1015
Set5
1015
Reset5
1015
Recovery Time Set5
1015
Reset 51015
tf Clock Input Rise or Fall 5tr, Time10
15
Maximum Clock Input 5fCL
Frequency10
15
µs
µs
elos terP)s(tcudoO -elosbrP tetcudo )(sns
ns
µs
ns
ns
ns
µs
µs
µs
Unlimited0.5
1.52.5
135
µs
MHz
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
7/13
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HCF4536B
TYPICAL APPLICATIONS
Time Internal Configuration Using External Clock; Set and Clock Inhibit Functions
Time Internal Configuration Using On-Chip RC oscillator and Reset Input to Initiate Time Interval
Time Internal Configuration Using Ext. Ck; Reset and Output Monostable to Achieve a Pulse Out Use of HCF4098B and HCF4536B to get Decode Pulse 8 Clock Pulses after Reset Pulses
TIMING DIAGRAM
bOelos terP)s(tcudoO -elosbrP tetcudo )(s8/13
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HCF4536B
FUNCTIONAL TEST SEQUENCE
Inputs
In 1HHLHLLLHL
SetLHHHHLLL
ResetHHHHHLLL
8-Bypass
HHHHHLLL
OutputsDecade Out Q1 Thru Q24
LLL
COMMENTS
All 24 steps are in reset modeCounter is in three 8-stage section in parallel
mode
First \"H\" to \"L\" Transition of Clock255 \"H\" to \"L\" transitions are clocked in the
counter
HHHL
The 255 \"H\" to \"L\" Transition
Counter converted back to 24 stages in series
mode.Set and Reset must be connected together and simultaneously go from \"H\" to \"L\"
In1 switches to a \"H\"Counter Ripples from an all \"H\" state to an all
\"L\" state
FUNCTIONAL TEST SEQUENCE
Test function has been included for the reduction of test time required to exercise all 24 counter stages.This test function divides the counter into three 8-stage section and 255 counts are loaded in each of the 8-stage sections in parallel. All TEST CIRCUIT
flip-flops are now at a \"H\". The counter is now returned to the normal 24-steps in series
configuration. One more pulse is entered into In1 which will cause the counter to ripple from an all \"H\" state to an all \"L\" state.
bOelos terP)s(tcudoO -elosbrP tetcudo )(sCL = 50pF or equivalent (includes jig and probe capacitance)RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
9/13
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HCF4536B
WAVEFORM : PROPAGATION DELAY TIMES, PULSE WIDTH CLOCK
bOelos terP)s(tcudoO -elosbrP tetcudo )(s10/13
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分销商库存信息:
STM
HCF4536BEY
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